Method for manufacturing complementary insulated gate field effect transistors
USRE31079E · kind E · reissue
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1980 |
| Grant date | Nov 16, 1982 |
| Priority date | — |
| Expiry date | Aug 29, 2000 |
Classification
- Technology area (CPC —)General
Abstract
Method for manufacturing .Iadd.semiconductor devices including, e.g., .Iaddend.complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using .Iadd.an oxidation-resistive material, e.g. .Iaddend.a silicon nitride layer.Iadd., .Iaddend.as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.