Burst-error correcting system
USRE31666E · kind E · reissue
5Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1983 |
| Grant date | Sep 11, 1984 |
| Priority date | — |
| Expiry date | May 6, 2003 |
Classification
- Technology area (CPC —)General
Abstract
In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a modulo 2 adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a modulo-2 adder to produce a second parity signal. The predetermined number of words of information signals and first and second parity signals are serially transmitted through a transmission line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.