Data dependency collapsing hardware apparatus
USRE35311E · kind E · reissue
13Cited by
8References
46Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 18, 1994 |
| Grant date | Aug 6, 1996 |
| Priority date | — |
| Expiry date | Aug 18, 2014 |
Classification
- Technology area (CPC —)General
Abstract
A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.