Logic array having high frequency internal clocking

USRE35797E · kind E · reissue

Assignee

• TriQuint Semiconductor, Inc. · US

Inventors

• Andrew C. Graham · Sunnyvale, US
• Michael G. France · Portland, US
• Robert C. Burd · Santa Clara, US
• Mark E. Fitzpatrick · San Jose, US

Key dates

• Filing date: Apr 19, 1995
• Grant date: May 19, 1998
• Expiry date: Apr 19, 2015

Classification

• Technology area (CPC —): General

Abstract

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.