Dynamic video RAM incorporating single clock random port control
USRE35921E · kind E · reissue
2Cited by
52References
76Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 8, 1994 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Aug 8, 2014 |
Classification
- Technology area (CPC —)General
Abstract
An architecture for a single chip dynamic video random access memory using a single clock to operate the random port to perform refresh, memory address, and to control the internal circuitry for inputting data and addresses and for outputting data as well as modifying information in the memory circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information In the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video Information between selected START and STOP bit locations within the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.