Configuration data loopback in a bus bridge circuit
USRE36191E · kind E · reissue
117Cited by
5References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1996 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Dec 19, 2016 |
Classification
- Technology area (CPC —)General
Abstract
A method and apparatus for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers. The host bridge circuit "bridges" all I/O accesses received over a host bus directly to a peripheral component bus without any decoding. The CDC is both initiator and target on the peripheral component bus for I/O access cycles generated by the host bridge circuit that are targeted for a host bridge configuration register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.