Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit
USRE36292E · kind E · reissue
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Sep 7, 1999 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC —)General
Abstract
The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.