Dual channel readback recovery system
USRE36671E · kind E · reissue
2Cited by
4References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1994 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Mar 4, 2014 |
Classification
- Technology area (CPC —)General
Abstract
A dual channel readback recovery circuit includes a high resolution channel and a low resolution channel and a data latch. A logical filter in one or both channels rejects signals that are followed by other signals if they are spaced apart less than the rejection time interval allowed by the code used. Polarity qualifying logic rejects signals in the channel that are not matched in polarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.