Method and apparatus for reducing power consumption in digital electronic circuits
USRE36839E · kind E · reissue
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC —)General
Abstract
An integrated circuit with power conservation includes a number of functional blocks, each of which includes a digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumpt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.