Heuristic processor
USRE37488E · kind E · reissue
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1996 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Dec 18, 2016 |
Classification
- Technology area (CPC —)General
Abstract
A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a nonlinear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least mean squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed to provide estimates of unknown result. The processor is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.