Large die photolithography
USRE38126E1 · kind E1 · reissue
5Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Jan 6, 2020 |
Classification
- Technology area (CPC —)General
Abstract
An improved reticle (20) and method of using it to expose layers of wafers for large integrated circuits (10). The integrated circuit (10) is designed so that nonrepeating patterns are laid out in perimeter areas, distinct from the center area containing contiguous repeating patterns. The reticle (20) is patterned with multiple masks (21-23), with different masks representing the repeating and nonrepeating patterns. The mask (22) representing the repeating pattern may then be stepped and illuminated separately from any mask (21, 23) representing a nonrepeating pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.