Instruction converting apparatus using parallel execution code

USRE41751E1 · kind E1 · reissue

Assignee

• PANASONIC HOLDINGS CORPORATION · JP

Inventors

• Taketo Heishi · Osaka, JP
• Tetsuya Tanaka · Shizuoka, JP
• Nobuo Higaki · Osaka, JP
• Shuichi Takayama · Ann Arbor, US
• Kensuke Odani · Kyoto, JP

Key dates

• Filing date: Nov 24, 2003
• Grant date: Sep 21, 2010
• Expiry date: Nov 24, 2023

Classification

• Technology area (CPC —): General

Abstract

A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.