Delay circuit and method
USRE42250E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Aug 10, 2021 |
Classification
- Technology area (CPC —)General
Abstract
A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.