Circuit and method for processing communication packets and valid data bytes
USRE43218E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2008 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Jun 27, 2028 |
Classification
- Technology area (CPC —)General
Abstract
Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.