Systems and methods for load detection and correction in a digital amplifier
USRE43461E1 · kind E1 · reissue
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2029 |
Classification
- Technology area (CPC —)General
Abstract
Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.