Forming transistor gate structures in a semiconductor using a mask layer over an insulating layer

USRE47227E1 · kind E1 · reissue

Assignee

• LONGITUDE LICENSING LIMITED · IE

Inventor

• Takeshi Ohgami · Tokyo, JP

Key dates

• Filing date: Jul 2, 2015
• Grant date: Feb 5, 2019
• Expiry date: Jul 2, 2035

Classification

• Technology area (CPC —): General

Abstract

A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.