Testing a circuit in a semiconductor device

USRE49390E1 · kind E1 · reissue

Assignee

• LONGITUDE LICENSING LIMITED · IE

Inventor

• Yoshiro Riho · Tokyo, JP

Key dates

• Filing date: Feb 3, 2020
• Grant date: Jan 24, 2023
• Expiry date: Feb 3, 2040

Classification

• Technology area (CPC —): General

Abstract

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.