Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same
USRE49780E1 · kind E1 · reissue
0Cited by
15References
65Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC —)General
Abstract
A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.