Adithya B. S.
1Patents
0h-index
9Co-inventors
19Inventor score
Filing activity: Sep 27, 2017 → Sep 27, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11257560B2 | Test architecture for die to die interconnect for three dimensional integrated circuits | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.