Patent · US Active

Test architecture for die to die interconnect for three dimensional integrated circuits

US11257560B2 · kind B2 · utility

0Cited by

1References

9Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sreejit Chakravarty · Mountain View, US
Fei Su · Bellevue, US
Puneet Gupta · Singapore, SG
Wei Ming Lim · Bayan Lepas, MY
Terrence Huat Hin Tan · Georgetown, US
Amit Sanghani · San Jose, US
Anubhav Sinha · Hyderabad, IN
Sudheer V Badana · Srikakulam, IN
Rakesh Reddy Kandula · Survanagiri, IN
Adithya B. S. · Bengaluru, IN

Key dates

Filing date	Sep 27, 2017
Grant date	Feb 22, 2022
Priority date	—
Expiry date	Feb 26, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2225/06565
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.