Inventor · San Diego, CA, US

Alessandro Risso

16Patents
3h-index
22Co-inventors
60Inventor score

Filing activity: May 14, 2002 → Mar 29, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7290081B2 Apparatus and method for implementing a ROM patch using a lockable cache Physics 25 Expired
US8745466B2 Detecting data-write errors Physics 21 Active
US8996967B2 Rendering data write errors detectable Electricity 19 Active
US10103843B1 On the fly interleaving/rate matching and deinterleaving/de-rate matching for 5G NR Electricity 3 Active
US10700829B2 Combining decision metrics of a scrambled payload Electricity 2 Active
US8510642B2 System and method for map detector for symbol based error correction codes Electricity 1 Active
US8379339B2 Closely coupled vector sequencers for a read channel pipeline Physics 1 Active
US10887053B1 Techniques for decoding downlink control information with different sizes in wireless communications Electricity 0 Active
US11784749B2 Polar coding Reed-Muller node optimization using Fast Hadamard Transform Electricity 0 Active
US9450618B2 Max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method Electricity 0 Active
US11870576B2 Control of error correction decoder operation and usage in a receiver device Electricity 0 Active
US11595177B2 Tone classification for physical channels with multiplexed data Electricity 0 Active
US11152953B2 Error detection for a wireless channel Electricity 0 Active
US11418294B2 Single step in-place operation method for 5G NR de-interleaving, de-rate matching, and HARQ combination Electricity 0 Active
US11496243B1 Techniques for masking and unmasking cyclic redundancy check bits for early termination of decoding Electricity 0 Active
US8694877B2 Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.