Control of error correction decoder operation and usage in a receiver device
US11870576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Mar 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0068
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for wireless communication is provided. The apparatus may be a receiver device that includes an error correction decoder, such as a low-density parity check (LDPC) decoder. The apparatus may achieve power savings and/or operation cycle savings by disabling the error correction decoder in scenarios where bits of a codeword in a signal transmission are received without errors. The apparatus obtains a first set of bits of a codeword, wherein the codeword includes the first set of bits and a second set of bits, and wherein the second set of bits is punctured. The apparatus recovers the second set of bits based on at least the first set of bits and determines whether to operate an error correction decoder based on a result of an error detection operation performed on the codeword using the first set of bits and the second set of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.