Alfons Vindasius
9Patents
9h-index
5Co-inventors
58Inventor score
Filing activity: Aug 21, 1997 → May 3, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5891761A | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform | Emerging Cross-Sectional Technologies | 83 | Expired |
| US6271598A | Conductive epoxy flip-chip on chip | Electricity | 71 | Expired |
| US6098278A | Method for forming conductive epoxy flip-chip on chip | Emerging Cross-Sectional Technologies | 57 | Expired |
| US6080596A | Method for forming vertical interconnect process for silicon segments with dielectric isolation | Emerging Cross-Sectional Technologies | 50 | Expired |
| US6255726A | Vertical interconnect process for silicon segments with dielectric isolation | Emerging Cross-Sectional Technologies | 46 | Expired |
| US7535109B2 | Die assembly having electrical interconnect | Electricity | 32 | Active |
| US6177296A | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform | Emerging Cross-Sectional Technologies | 30 | Expired |
| US6124633A | Vertical interconnect process for silicon segments with thermally conductive epoxy preform | Emerging Cross-Sectional Technologies | 29 | Expired |
| US8357999B2 | Assembly having stacked die mounted on substrate | Electricity | 14 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.