Inventor · Noida, IN

Barsneya Chakrabarti

4Patents
1h-index
11Co-inventors
37Inventor score

Filing activity: Mar 8, 2013 → Jul 27, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US9201992B2 Method and apparatus using formal methods for checking generated-clock timing definitions Physics 1 Active
US9721058B2 System and method for reactive initialization based formal verification of electronic logic design Physics 1 Active
US8656328B1 System and method for abstraction of a circuit portion of an integrated circuit Physics 0 Active
US10599800B2 Formal clock network analysis, visualization, verification and generation Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.