Method and apparatus using formal methods for checking generated-clock timing definitions
US9201992B2 · kind B2 · utility
1Cited by
8References
16Claims
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Key dates
| Filing date | Feb 19, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Mar 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.