Bhaarath Kumar
4Patents
2h-index
2Co-inventors
27Inventor score
Filing activity: Oct 29, 2013 → Sep 12, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10042692B1 | Circuit arrangement with transaction timeout detection | Physics | 3 | Active |
| US9465766B1 | Isolation interface for master-slave communication protocols | Physics | 2 | Active |
| US10657067B1 | Memory management unit with prefetch | Physics | 2 | Active |
| US10402332B2 | Memory pre-fetch for virtual memory | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.