Memory management unit with prefetch
US10657067B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2016 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Sep 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.