Chakrapani Pathikonda
10Patents
7h-index
5Co-inventors
51Inventor score
Filing activity: Mar 22, 1996 → May 31, 2000
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6208180A | Core clock correction in a 2/N mode clocking scheme | Physics | 110 | Expired |
| US5862373A | Pad cells for a 2/N mode clocking scheme | Physics | 22 | Expired |
| US5802132A | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme | Physics | 19 | Expired |
| US6061599A | Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair | Physics | 19 | Expired |
| US6268749A | Core clock correction in a 2/n mode clocking scheme | Physics | 18 | Expired |
| US5834956A | Core clock correction in a 2/N mode clocking scheme | Physics | 8 | Expired |
| US5826067A | Method and apparatus for preventing logic glitches in a 2/n clocking scheme | Physics | 8 | Expired |
| US6104219A | Method and apparatus for generating 2/N mode bus clock signals | Physics | 7 | Expired |
| US6114887A | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme | Physics | 6 | Expired |
| US5821784A | Method and apparatus for generating 2/N mode bus clock signals | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.