Core clock correction in a 2/N mode clocking scheme
US5834956A · kind A · utility
8Cited by
88References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.