Ed Seewann
5Patents
3h-index
6Co-inventors
39Inventor score
Filing activity: Feb 11, 2005 → Dec 7, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7283404B2 | Content addressable memory including a dual mode cycle boundary latch | Physics | 9 | Expired |
| US7167385B2 | Method and apparatus for controlling the timing of precharge in a content addressable memory system | Physics | 5 | Expired |
| US7116569B2 | Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask | Physics | 4 | Expired |
| US7600071B2 | Circuit having relaxed setup time via reciprocal clock and data gating | Physics | 0 | Active |
| US7501854B2 | True/complement generator having relaxed setup time via self-resetting circuitry | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.