Circuit having relaxed setup time via reciprocal clock and data gating
US7600071B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 7, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Nov 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a circuit output, a data input that receives a data signal, and a clock input that receives a clock signal. The integrated circuit further includes first and second logic gates. The first logic gate has a first input coupled to the clock input, a second input coupled to the data input, and an output and a second logic gate. The second logic gate has a first input coupled to the data input, a second input coupled to the output of the first logic gate, and an output coupled to the circuit output. Setup time of the data signal relative to the clock signal at the second logic gate is improved by reciprocal gating of the data and clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.