Elise Baylac
2Patents
1h-index
7Co-inventors
30Inventor score
Filing activity: Oct 28, 2014 → Dec 22, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10263110B2 | Method of forming strained MOS transistors | Electricity | 1 | Active |
| US9543214B2 | Method of forming stressed semiconductor layer | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.