Method of forming strained MOS transistors
US10263110B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 22, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jan 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.