Iris Sorani
6Patents
2h-index
14Co-inventors
44Inventor score
Filing activity: Jun 30, 2005 → Jun 17, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9830272B2 | Cache memory staged reopen | Emerging Cross-Sectional Technologies | 7 | Active |
| US9081687B2 | Method and apparatus for MONITOR and MWAIT in a distributed cache architecture | Physics | 7 | Active |
| US8281083B2 | Device, system and method of generating an execution instruction based on a memory-access instruction | Physics | 2 | Expired |
| US9239789B2 | Method and apparatus for monitor and MWAIT in a distributed cache architecture | Physics | 1 | Active |
| US9063729B2 | Device, system and method of generating an execution instruction based on a memory-access instruction | Physics | 0 | Active |
| US9720843B2 | Access type protection of memory reserved for use by processor logic | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.