Patent · US Active

Cache memory staged reopen

US9830272B2 · kind B2 · utility

7Cited by

4References

26Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Iris Sorani · Nahariah, IL
Larisa Novakovsky · Haifa, IL
Joseph Nuzman · Aberdeen, US

Key dates

Filing date	Dec 28, 2011
Grant date	Nov 28, 2017
Priority date	—
Expiry date	Apr 23, 2032

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.