Jigar Vora
16Patents
3h-index
18Co-inventors
49Inventor score
Filing activity: Jun 23, 2010 → Jan 23, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9426185B1 | Proximity based communication with embedded system | Electricity | 18 | Active |
| US11258671B1 | Functionality management for devices | Electricity | 11 | Active |
| US8345490B2 | Split voltage level restore and evaluate clock signals for memory address decoding | Physics | 3 | Active |
| US10484512B2 | Management of multi-radio gateway device using virtual gateway device | Electricity | 2 | Active |
| US8599642B2 | Port enable signal generation for gating a memory array device output | Physics | 2 | Active |
| US10404832B2 | Management of gateway device using virtual gateway device | Electricity | 1 | Active |
| US10129226B2 | Proximity based communication with embedded system | Electricity | 0 | Active |
| US9977485B2 | Cache array with reduced power consumption | Emerging Cross-Sectional Technologies | 0 | Active |
| US9355692B2 | High frequency write through memory device | Physics | 0 | Active |
| US8861284B2 | Increasing memory operating frequency | Physics | 0 | Active |
| US10223160B2 | Compact schedules for resource-constrained devices | Physics | 0 | Active |
| US10805279B2 | Communication module for embedded system | Electricity | 0 | Active |
| US8351278B2 | Jam latch for latching memory array output data | Physics | 0 | Active |
| US8345497B2 | Internal bypassing of memory array devices | Physics | 0 | Active |
| US9971394B2 | Cache array with reduced power consumption | Emerging Cross-Sectional Technologies | 0 | Active |
| US10949255B2 | Compact schedules for resource-constrained devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.