High frequency write through memory device
US9355692B2 · kind B2 · utility
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2References
3Claims
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Key dates
| Filing date | Sep 18, 2012 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.