Jovanka Ciric
2Patents
2h-index
2Co-inventors
27Inventor score
Filing activity: Dec 4, 2002 → Dec 1, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6973632B1 | Method and apparatus to estimate delay for logic circuit optimization | Physics | 24 | Expired |
| US7434187B2 | Method and apparatus to estimate delay for logic circuit optimization | Physics | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.