Method and apparatus to estimate delay for logic circuit optimization
US7434187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2005 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Jun 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.