Keyur Payak
5Patents
2h-index
13Co-inventors
37Inventor score
Filing activity: Jun 11, 2020 → May 25, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10998816B1 | On-chip determination of charge pump efficiency using a current limiter | Emerging Cross-Sectional Technologies | 5 | Active |
| US11335411B1 | Erase operation for memory device with staircase word line voltage during erase pulse | Electricity | 4 | Active |
| US11927635B2 | Determining charge pump efficiency using clock edge counting | Electricity | 0 | Active |
| US12046297B2 | Method to optimize first read versus second read margin by switching boost timing | Electricity | 0 | Active |
| US11758718B2 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.