Method to optimize first read versus second read margin by switching boost timing
US12046297B2 · kind B2 · utility
0Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2022 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Sep 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.