Kieu Do
14Patents
4h-index
7Co-inventors
53Inventor score
Filing activity: Feb 19, 1992 → Nov 3, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5353235A | Wire length minimization in channel compactor | Physics | 50 | Expired |
| US5399517A | Method of routing three layer metal gate arrays using a channel router | Emerging Cross-Sectional Technologies | 14 | Expired |
| US9316689B2 | Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models | Physics | 10 | Active |
| US9874608B2 | Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models | Physics | 5 | Active |
| US9651619B2 | Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models | Physics | 4 | Active |
| US9689921B2 | Testing SoC with portable scenario models and at different levels | Physics | 2 | Active |
| US10365326B2 | Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models | Physics | 2 | Active |
| US9310433B2 | Testing SOC with portable scenario models and at different levels | Physics | 1 | Active |
| US11748240B2 | Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models | Physics | 0 | Active |
| US9360523B2 | Display in a graphical format of test results generated using scenario models | Physics | 0 | Active |
| US10429442B2 | Testing SOC with portable scenario models and at different levels | Physics | 0 | Active |
| US10838006B2 | Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models | Physics | 0 | Active |
| US11113184B2 | Display in a graphical format of test results generated using scenario models | Physics | 0 | Active |
| US11055212B2 | Testing SoC with portable scenario models and at different levels | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.