Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario models
US9316689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2015 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.