Inventor · San Jose, CA, US

Manjunath D. Haritsa

3Patents
3h-index
9Co-inventors
36Inventor score

Filing activity: Feb 4, 2000 → Oct 17, 2001

Most-cited inventions

PatentTitleAreaCited byStatus
US6665845B1 System and method for topology based noise estimation of submicron integrated circuit designs Physics 58 Expired
US6587815B1 Windowing scheme for analyzing noise from multiple sources Physics 15 Expired
US6941532B2 Clock skew verification methodology for grid-based design Physics 11 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.