System and method for topology based noise estimation of submicron integrated circuit designs
US6665845B1 · kind B1 · utility
58Cited by
2References
6Claims
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Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Dec 16, 2003 |
| Priority date | — |
| Expiry date | Jul 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tool for computing noise coupled onto victim lines from aggressor lines of an integrated circuit has code for traversing a victim line of the integrated circuit layout to measure its length, its average width, a coupling length, and a harmonic mean of spacing between the victim line and aggressor lines. The tool has code for computing a resistance, estimated coupling capacitance, and total capacitance of the victim line from these parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.