Michael A. Simone
4Patents
4h-index
7Co-inventors
33Inventor score
Filing activity: Mar 3, 1995 → Sep 5, 1995
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5651124A | Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state | Physics | 46 | Expired |
| US5784586A | Addressing method for executing load instructions out of order with respect to store instructions | Physics | 18 | Expired |
| US5745726A | Method and apparatus for selecting the oldest queued instructions without data dependencies | Physics | 16 | Expired |
| US5638312A | Method and apparatus for generating a zero bit status flag in a microprocessor | Physics | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.