Michel Bron
13Patents
11h-index
12Co-inventors
69Inventor score
Filing activity: Mar 30, 1988 → Jun 22, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7085156B2 | Semiconductor memory device and method of operating same | Physics | 334 | Expired |
| US7733693B2 | Semiconductor memory device and method of operating same | Physics | 215 | Active |
| US7085153B2 | Semiconductor memory cell, array, architecture and device, and method of operating same | Physics | 213 | Expired |
| US7187581B2 | Semiconductor memory device and method of operating same | Physics | 102 | Expired |
| US7542340B2 | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same | Physics | 95 | Active |
| US5557743A | Protection circuit for a microprocessor | Physics | 43 | Expired |
| US7359229B2 | Semiconductor memory device and method of operating same | Physics | 33 | Active |
| US4841133A | Data card circuits | Physics | 24 | Expired |
| US6128224A | Method and apparatus for writing an erasable non-volatile memory | Physics | 21 | Expired |
| US4910393A | Memory cards | Physics | 21 | Expired |
| US6075727A | Method and apparatus for writing an erasable non-volatile memory | Physics | 13 | Expired |
| US7969779B2 | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same | Physics | 8 | Active |
| US8395937B2 | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.