Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US7969779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2009 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Jul 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.