Naresh Patel
10Patents
7h-index
11Co-inventors
59Inventor score
Filing activity: Aug 26, 2005 → May 2, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8578386B1 | Processor scheduling method and system using domains | Emerging Cross-Sectional Technologies | 35 | Active |
| US7430639B1 | Optimization of cascaded virtual cache memory | Physics | 24 | Expired |
| US7424577B2 | Dynamic optimization of cache memory | Emerging Cross-Sectional Technologies | 20 | Expired |
| US8015427B2 | System and method for prioritization of clock rates in a multi-core processor | Emerging Cross-Sectional Technologies | 20 | Active |
| US8112585B2 | Method and apparatus for dynamically switching cache policies | Physics | 12 | Active |
| US8255630B1 | Optimization of cascaded virtual cache memory | Physics | 9 | Active |
| US9405695B2 | Cache modeling using random sampling and a timestamp histogram | Physics | 8 | Active |
| US8176251B2 | Dynamic optimization of cache memory | Emerging Cross-Sectional Technologies | 6 | Active |
| US9146783B2 | Processor scheduling method and system using domains | Emerging Cross-Sectional Technologies | 0 | Active |
| US10686906B2 | Methods for managing multi-level flash storage and devices thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.