Inventor · San Jose, CA, US

Philippe Sarrazin

3Patents
2h-index
3Co-inventors
37Inventor score

Filing activity: May 30, 2008 → Jun 20, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US8407650B1 Method for repeated block modification for chip routing Physics 14 Active
US10318691B2 Timing analysis and optimization of asynchronous circuit designs Physics 2 Active
US8893070B2 Method for repeated block modification for chip routing Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.